1. Field of the Invention
This invention relates to an improved type of control unit for electronic microcontrollers or microprocessors, and, more specifically, relates to a control unit that includes a finite state machine having at least one combinational logic network. The invention also relates to a method of fabricating a control unit for electronic microcontrollers or microprocessors.
2. Description of the Related Art
Microcontrollers or microprocessors typically include: a resource-managing central block provided inside a so-called device “core”, and a set of peripheral blocks connected to the central block.
The managing central block is commonly referred to as the CU (Control Unit). A CU unit oversees all the operative phases of the microcontroller or microprocessor, and clocks the carrying out of some internal operations.
In programmable devices, the CU performs, in principle, the exemplary operations including: pointing to a memory location which contains a program row to be executed; decoding the instruction thereof; carrying out the operations included in the decoded instruction; and pointing to the next program row.
The complexity of devices based on a microcontroller or microprocessor is increasing, and this reflects in the device having to carry out a larger number of different operations, among which are the following: transmitting data between the device and the outside; executing logic-arithmetic functions; conditional or unconditional skip operations, and subroutine calls; controlling interrupt signals; and establishing special flows of operations, as is the case with microcontrollers or microprocessors designed for special applications, such as dedicated microcontrollers for fuzzy logic computations.
Thus, when the number of instructions, and hence the computational capacity of the device to be designed increases, so does the hardware complexity of the CU. The unit becomes more complex because of the number of the instructions and the necessity to deliver the appropriate sequence of control signals for the device to operate correctly. Further, the CU must retain its capability to operate in an exclusive manner where special asynchronous interrupt signals are required.
Present designs for microcontrollers or microprocessors, as well as for ASIC (Application Specific Integrated Circuit) devices follow descriptive criteria.
In other words, the circuit, instead of being designed by connecting circuit-wise such standard subunits as logic gates to perform certain logic operations (AND, OR, NOT, etc.) in order to provide complex functions of relational operators, is defined by means of a descriptive language based on peculiar syntax and semantics.
One of these description languages is known by the acronym VHDL (VHSIC Hardware Description Language, where VHSIC stands for Very High Speed Integrated Circuit). This language provides the designer with powerful tools for translating the notional idea into a functional description, simulating the block thus described, and for converting the behavior description into a RTL (Register Transfer Level) scheme, among other abilities.
The specifications for a block operation are formalized using the VHDL language in a listing. The integrated circuit design environments, such as those known in the trade as Cadence, Synopsys, etc., allow for the creation of symbols, their behavior description, and ensuing simulation. The latter is aimed at investigating the correct operation of the block just described.
A proper behavior description can later be translated to a RTL, using compilers which synthesize the circuit to obtain a schematic consisting of a set of elementary logic gates.
The exemplary designing method outlined hereinabove is currently widely used for progressing from the notional idea to a hard implementation. However, it cannot solve the problem of providing highly complex functions.
As would be expected, if the circuit is to perform many functions, the corresponding VHDL listing becomes very complex and exceedingly long.
In a simplistic way, it could be thought that this is merely a problem of listing size. Row-wise complex and bulky listings are indeed more difficult to set up, involve time-consuming checking procedures for servicing and modifying parts of it, and result in execution times which are directly proportional to their length in the respect of simulations and circuit “syntheses”.
CUs provide a fair example of how the functional characteristics of a block turn into VHDL listings of a size and complexity which exceeds that of any other blocks within a microcontroller or microprocessor.
The overall construction of a FSM (Finite State Machine) basically comprises two combinational logic networks relating to the future state of the machine and the current outputs, as well as a sequential portion made up of a set of flip-flop memory cells for storing up given state vectors.
The combination of the inputs and the vector representing the “present state” of the state machine generates a “future state” vector that constitutes the data to be stored in the state memory cells. The outputs from these flip-flop cells retain the value of the present state, which is fed back to the combinational network for determining the value of the future state and is simultaneously supplied to a section of the current outputs. The output section issues new outputs of its own dependent on the present state, and occasionally inputs as well, as shown schematically in the accompanying FIG. 1.
Considering the complex circuit and functional aspects of a control unit, it can be appreciated that this prior approach using a finite state machine involves highly complex VHDL listings, especially with respect to the combinational networks.
Until now, no control units for microcontrollers or microprocessors have the necessary structural and functional features as to simplify the unit designing stage to the utmost degree and overcome the limitations of prior art solutions.